1. Field of the Invention
The present invention relates to frequency synthesizers used in the front end of an RF receiver system. More particularly, the present invention relates to frequency synthesizer circuits for use in frequency-hopped spread-spectrum systems that use a dual phase-locked loop architecture to provide feedback control for VCO phase noise in increments that are not directly dependent upon the loop bandwidth of either of the phase-locked loops used within the synthesizer.
2. Prior Art Statement
As RF systems become more sophisticated and are applied to a wider range of applications, the need increases for RF systems that are economical to produce and yet are applicable to complex spread-spectrum applications. Frequency synthesizers are widely used in RF front end systems. For sophisticated applications, the output of the frequency synthesizer must satisfy stringent performance requirements, wherein the frequency synthesizer must be able to generate a large number of closely-spaced channels. For example, the Groupe Speciale Mobile (GSM) RF system, which acts as a mobile telephone standard in Europe, requires 124 channels to be generated with a 200 kHz spacing. In a more complex IS54 mobile telephone application, 800 channels are required with only a 30 kHz spacing. Furthermore, in addition to generating distinct closely spaced channels, a frequency synthesizer must be able to exhibit a relatively fast lock when switching from one channel to another.
Many conventional frequency synthesizers employ a single pulse-swallow frequency divider within a phase-locked loop, in order to obtain precise channel selection in the output frequency. Such prior art systems are exemplified by U.S. Pat. No. 4,380,743 to Underhill et al., entitled FREQUENCY SYNTHESIZER OF THE PHASE LOCK LOOP TYPE; U.S. Pat. No. 4,599,579 to McCann, entitled FREQUENCY SYNTHESIZER HAVING JITTER COMPENSATION; and U.S. Pat. No. 5,361,044 to Norimatu et al., entitled PHASE LOCKED LOOP FREQUENCY SYNTHESIZER. The use of such single loop synthesizer configurations has the advantage of exhibiting small side bands at the output of the voltage controlled oscillator. Another advantage is that such synthesizer configurations are relatively low in complexity.
A disadvantage of such conventional single loop frequency synthesizers is that the lock time of the loop tends to be quite long. This makes conventional single loop frequency synthesizers a poor selection for high performance applications such the frequency-hopped spread-spectrum systems used in sophisticated mobile telephone applications. A more critical disadvantage of such conventional frequency synthesizers is that the feedback within such a single loop circuit is incapable of correcting the phase noise of the voltage controlled oscillator outside the loop bandwidth. This disadvantage is most prevalent in monolithic implementations because integrated oscillators typically do not incorporated passive resonators and therefore produce large phase noise.
It is therefore an object of the present invention to provide a frequency synthesizer circuit that utilizes monolithic integration in mainstream VLSI technologies wherein the frequency synthesizer is capable of correcting the phase noise of the voltage controlled oscillator outside the loop bandwidth.
It is a further objective of the present invention to provide a frequency synthesizer circuit with improved lock time between distinct channels, thereby enabling the circuit to be more readily adapted to high frequency-hopped spread-spectrum applications.